1. Field of the Invention
This invention relates to semiconductor devices and more particular to a trenched field effect transistor especially suitable for low voltage switching applications.
2. Description of the Prior Art
Field effect transistors (FETs) are well known, as are metal oxide semiconductor field effect transistors (MOSFETs); such transistors are often used for power applications. There is a need for power transistors for relatively low voltage applications, i.e. typically under 50 volts, that have low current leakage blocking capability.
Examples of trench field effect transistors suitable for such applications are disclosed in "Comparison of Ultra Low Specific On Resistance UMOSFET Structures . . . " by Syau et al., IEEE Transactions on Electron Devices, Vol. 41, No. 5, May 1994. Inter alia, this publication describes the so-called INVFET structure of present FIG. 1, which corresponds to FIG. 1(b) of the publication. Present FIG. 1 shows only a portion of a single transistor including the polysilicon (polycrystalline silicon) gate electrode 10 which in this case is N-type polysilicon which is insulated by a gate oxide layer 12 on its sides and bottom in a trench 14 and insulated on its top side by an oxide layer 18. The trench 14 extends through the N+ doped source region 22 through the P doped base region 24 and into the N+ doped drain region 26. The drain electrode 30 is formed on the underside of the drain region 26 and the source electrode 32 formed on the top side of the source region.
Also described in FIG. 1(c) of this article and shown here in present FIG. 2 is the somewhat similar so-called EXTFET which is identical to the INVFET except for having an additional N- doped drift region 36 formed underlying the P doped base region 24. For both of these devices the P base region 24 is formed by diffusion (hence does not exhibit uniform doping) and is fairly heavily doped. It is believed that a typical surface concentration of the P base region 24 is 10.sup.17 /cm.sup.3.
These devices are both intended to avoid full depletion of the P base (body) region 24. They each have the gate electrode 10 doped to the same conductivity type as is the drain region 26 (i.e. N type) as shown in FIGS. 1 and 2. The "mesa" width, i.e. the width of the source region between two adjacent trenches, is typically 3 .mu.m and a typical cell pitch for an N-channel device is about 6 .mu.m. Blocking is accomplished by a quasi-neutral (undepleted) PN junction at a V.sub.gs (gate source voltage) of zero. The ACCUFET (see Syau et al. article) offers the best specific on resistance at the expense of poor blocking capability, while the INVFET and EXTFET offer improved blocking at the expense of increased specific on resistance.
As is well known, a power MOSFET should have the lowest possible on-state specific resistance in order to minimize conduction losses. On-state resistance is a well known parameter of the efficiency of a power transistor and is the ratio of drain-to-source voltage to drain current when the device is fully turned on. On-state specific resistance refers to resistance times cross sectional area of the substrate carrying the drain current.
However, these prior art devices do not provide the optimum low on-state specific resistance in combination with blocking state low current leakage.